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[dsp] Analog front end design

scott at opentrac.org scott at opentrac.org
Thu Apr 21 16:29:31 UTC 2005


Generally, wouldn't you want the sample rate to be a multiple of the baud
rate to avoid ISI when you're filtering?  Or maybe I'm just designing my
filters wrong.  Seems like it'd make clock recovery simpler, too.

Anyway, I'm trying something along the lines of what you're suggesting, I
think.  Right now it's just a test program on the PC.  It's multiplying each
sample in the input waveform by a sample 90 degrees apart at 1700 hz.
Haven't got the LPF implemented properly yet.  I set it up to output a
digital value based on a couple of thresholds and I can plot the result in
Excel and see the bits clearly.  It's not going to handle much noise that
way, though.

Can you suggest a good book that would cover this?  Preferably something
accessible to a relative newbie.  =]

Scott

-----Original Message-----
From: dsp-bounces at lists.tapr.org [mailto:dsp-bounces at lists.tapr.org]On
Behalf Of David Willmore
Sent: Wednesday, April 20, 2005 9:47 PM
To: TAPR DSP Mailing List
Subject: Re: [dsp] Analog front end design


> I was looking at a nice dual-channel 16-bit CODEC from ADI (AD73322L), but
> the problem I ran into with that chip is that it has a limited selection
of
> sample rates, and they're not baud rate multiples.  Maybe the clock could
be
> changed, but I don't know enough about sigma-delta ADC design to know if
> that's really a good idea.  Another possibility is to use the MCU's
on-board
> ADC, but it would require the addition of a buffer and it'll only do 10
bits
> of resolution.  I'm not sure that'll give enough dynamic range, especially
> if I need to do much filtering in software.

What's baud rate got to do with it? :)

1200 baud AFSK decode:
AD > complex mix with 1700 Hz tone > 600 Hz LPF > ArcTan > clock
recovery/data decode

Good to hear from you, Scott.

Cheers,
David

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