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[dsp] Analog front end design

Mark mark at cpovo.net
Thu Apr 21 18:10:05 UTC 2005

On 21 Apr 2005 at 9:29, scott at opentrac.org wrote:

> It's multiplying each sample in the input waveform by a sample 90 degrees
> apart at 1700 hz. 

	Last year I did some experiments with the Atmel ATMega8 processor
and used your approach to design a 1200bps AFSK modem. Later changed to 
the one used on the link below. It gives better decoding. 
	I did the 1200bps decoding using 16bit fixed-point math running at 
6.144MHz. Lots of power in that Atmel uP!


	BTW, lots of good info on those pages:


	Mark Jordan, PY3SS

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