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[time-freq] Reflock Manual Update

Mark Miller markm at kramrellim.com
Fri Nov 4 14:52:18 UTC 2005


Steve,

I take it that I can't use my Xilinx JTAG programming cable?  I have the 
Xilinx Parallel Cable IV.

73,

Mark N5RFX

At 10:00 PM 11/3/2005, you wrote:
>Programming the CPLD requires a JTAG programmer (a parallel port to 10-pin
>header programmer) and the Quartus II PC software (you can download from the
>Altera web site).
>
>
>
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