[time-freq] Reflock II programming

[BOBBY]

Hi Lyle,

Long time no chat.

> The  absolute voltage limit on any pin of a MAX II device is34.6V, and the 
maximum recommended voltage is 3.3V.

I'm not sure if you meant 3.6V or 4.6V. I did notice the newer programming adapters supported
other voltages and in some cases buffering. Somewhere in the process of looking for the
byteblaster schematic on the altera website, I recall (perhaps wrongly) running across a 
statement that these parts were 5v logic tolerant. The choice seemed to be drive the CPLD 
side of the 244 too high, or the PC side too low. I've had pretty good luck with splitting the 
difference in the past by lowering Vcc. 

I wasn't paying enough attention to this project early on. Actually the project is to GPS discipline 
an Rb osc., the Reflock just seemed a good shortcut. So the byteblaster was made up for this project,
and that was only because I failed to notice the "complete kit" with the CPLD installed
doesn't have the CPLD programmed prior to soldering it down...  Foolishly I thought the different
configurations were selected with external configuration bits. 

Oh well, once I find out what and where the configuration bits are...
 
It also appears for this application only the (ones) R&N divider resistors need to be installed, but 
not any 0 ohm jumpers. That's based on all divider pins being default pulled low after programming.
I may install all the resistors anyway, since it would be faster than investigating to find out if they 
need to be there or not. 

Someday I'd like to get a block diagram with enough detail to figure out what the configuration
bits mentioned in my previous email actually do and where. But at least I now have a schematic that
shows LED's and other details resembling the board I have.

73 Bobby k4bga

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