Order Tray | Contact Us | Home | SIG Lists

[time-freq] A few clues

BOBBY ba at bobby.net
Sun Nov 20 22:37:37 UTC 2005

It may have been obvious to the folks involved in the design of the reflock II, but for this newcomer
a light has just come on. The schematic only represents ONE circuit, and it may not be the one you
have loaded into the cpld.

I'd like to offer a couple of suggestions to Steve etc.

Make a specific statement that the schematic enclosed is drawn for xx_xxxx_xx.pof and
pin functions may be different for other files supplied with this kit.


Copy Microchip's PICs and include alternate pin functions in their names, ie. RA0/C1in/Vref/ISPCLK 


Mention "The .pin file definitions may supercede the pin function and name shown on the schematic."

For those following along, let's have a look at how this applies to the r2_enhpps_20.txt file, which says:

-- conf=00 locks to 50KHz multiples      
-- conf=01 locks to 25KHz multiples
-- conf=10 locks to 12.5 KHz multiples
-- conf=11 locks to 10 KHz multiples  > Appears to mean N divider bits 1 and 2 no 0 jumpers installed.

the lock detector is not working properly....  > .pin file sets I/O pin states for LEDs to GND*  unused.
but this is the first time I had a chance
to see that code in action :)

note 1pps input is on P2 and REF input is left   > P6 for the June 28th 2005 PWBs in the kit.

pps_pol = 1 >> falling edge of 1pps is used
pps_pol = 0 >> rising edge of 1pps is used     > That would be R divider bit 0 for the rest of us.

Man are my shins getting tired.

73 Bobby  k4bga

-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://www.tapr.org/pipermail/time-freq/attachments/20051120/a952e0e6/attachment.htm 

More information about the time-freq mailing list