[time-freq] A few clues

[Steven Bible]

Hi Bobby,

Very good points.  In fact I was also coming from the Reflock I knowledge
base.

The design of the Reflock II is that it is one piece of hardware that has a
lot of flexibility depending on the programming of the CPLD.  What I have
been trying to document in the assembly/operations guide is this fact, and
it's not easy :-).  I think the best approach is to document the hardware
first.  Then document individually the various configurations.  For example,
if you want to do 1 PPS GPS, then do the following.  If you want to do a
reference lock, do this.

As you have learned, the *.pin file tells the the signal to CPLD pin number,
regardless of the schematic naming.  Trust in the *.pin file.

As we learn more, we can do a redesign of the Reflock II and make it easier
to set up and configure.  This is a bit of a learning process for us as
well.  Welcome to the bleeding edge! :-)

73,

- Steve, N7HPR
 (n7hpr at tapr.org)






-----Original Message-----
From: time-freq-bounces at lists.tapr.org
[mailto:time-freq-bounces at lists.tapr.org]On Behalf Of BOBBY
Sent: Sunday, November 20, 2005 3:38 PM
To: time-freq at lists.tapr.org
Subject: [time-freq] A few clues


It may have been obvious to the folks involved in the design of the reflock
II, but for this newcomer
a light has just come on. The schematic only represents ONE circuit, and it
may not be the one you
have loaded into the cpld.

I'd like to offer a couple of suggestions to Steve etc.

Make a specific statement that the schematic enclosed is drawn for
xx_xxxx_xx.pof and
pin functions may be different for other files supplied with this kit.

or

Copy Microchip's PICs and include alternate pin functions in their names,
ie. RA0/C1in/Vref/ISPCLK

or

Mention "The .pin file definitions may supercede the pin function and name
shown on the schematic."
----------

For those following along, let's have a look at how this applies to the
r2_enhpps_20.txt file, which says:

-- conf=00 locks to 50KHz multiples
-- conf=01 locks to 25KHz multiples
-- conf=10 locks to 12.5 KHz multiples
-- conf=11 locks to 10 KHz multiples  > Appears to mean N divider bits 1 and
2 no 0 jumpers installed.


the lock detector is not working properly....  > .pin file sets I/O pin
states for LEDs to GND*  unused.
but this is the first time I had a chance
to see that code in action :)

note 1pps input is on P2 and REF input is left   > P6 for the June 28th 2005
PWBs in the kit.
unconnected.

pps_pol = 1 >> falling edge of 1pps is used
pps_pol = 0 >> rising edge of 1pps is used     > That would be R divider bit
0 for the rest of us.



Man are my shins getting tired.

73 Bobby  k4bga