[time-freq] REFLOCK II questions

[Luis Cupido]

Hi Chris,

The actual division is affected by a
factor of 2 in both arms for the XOR phase comp to function properly,
and those are the signals being fed out to test.
So you will see always half of the expected frequency on the fout and rout.

The N number entering the CPLD sets the division rate to N+1

So you used N=1 division will be by 2 and the aditional factor of 2 makes it
dividing by 4.

So it is working as expected.

( this should be on the documentation somewhere, I will check...
if not there or not clear enought I will modify it)

Thanks.

Luis Cupido.


P.S. the VHDL files were not released yet.


  ----- Original Message ----- 
  From: Christopher Hoover 
  To: time-freq at lists.tapr.org 
  Cc: ch at murgatroid.com 
  Sent: Saturday, January 14, 2006 3:45 AM
  Subject: [time-freq] REFLOCK II questions


  Hi folks,

  I put a REFLOCK II kit together the other evening.   Nice design.  

  Several suggestions for the next revision if there is one: I would have like to have seen switches (there are nice low profile SMT DIP switches) for R and N and the use of resistor packs for the pull ups.  Ditto for PD; jumpers would be good here (2mm?).  Testpoints for the divided outputs would be valuable.

  Anyhow, I'm having a bit of trouble with the jumpers.

  I programmed the board with r2_flex_01 from r2_conf_nov05_02.  The MD5 hash of the pof is f91b4faaafd742cba4851a6c8ae28e17.

  Both ref and fin are fed by 10 MHz.   ref is from an extremely stable source (GPS-disciplined Rb oscillator).   fin is from an HP 10811A.

  Signals to the CPLD (pins 89 and 91) look good and are at precisely 10 MHz and ~10 MHz.

  I've got R set to (00 0)000.   I've got N set to 0000 0000 0001.

  The divided signals on pins 73 and 74 are 2.5 MHz (fout) and 50 KHz (rout).   That's division by 4 and 200.

  According to the documentation, I was expecting division by 100 (R=000) and division by 1 (N=0..01).

  A little help?

  ciao,
  -- Christopher.

  p.s where is the source for the pof files?  is it vhdl or verilog or something else?



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