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[time-freq] RE: time-freq Digest, Vol 4, Issue 2

Christopher Hoover ch at murgatroid.com
Mon Jan 16 03:06:34 UTC 2006

> The N number entering the CPLD sets the division rate to N+1

Gotcha.  Thats what I expected.

Attached is an Excel worksheet that will tell you how to set the jumpers for
the flex_01 pof.

I have the board working now.  It looks pretty good(*)  As the 10811A needs
an EFC from -5V to +5V, I had to set the frequency adjust a bit low, as the
EFC has a negative coefficient.

> P.S. the VHDL files were not released yet.

"yet"?   When will they be released?   I (and others, I suspect) would love
to hack on them.  I've done quite a lot of FPGA and CPLD design in VHDL.


(*)  I need to get my HPIB bus up so I can compute some long term Allan
variances with my 5370B and 5371A.
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