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[time-freq] TADD-3

Christopher Hoover ch at murgatroid.com
Mon Jul 10 03:29:38 UTC 2006

FYI, I either got a bad 74ACT14(*) or, equally likely, I blew one
section of a good one.  But, n.b.,  it didn't fail catastrophically: the
rise (fall) time of one gate was awful, making for large skews (80 ns!)
between the TADD-3 outputs.
Some thoughts on TADD-3 mark 2, if there is one:
1. I would love to see some (maybe optional) LED's on the board, perhaps
placed between the output BNC's, such that they could be seen after
packaging.   This would be useful for adjusting the comparators, but
good for sanity checks, too.  There are spare gates (IC3C and IC3D) that
might be used in conjunction with a simple pulse stretching circuit.
2. I would love to see an option for a differential PECL input.
Differential PECL is common in telecom disciplined-oscillator gear, e.g.
HP Z3801A.  I've hacked my TADD-3 with an MC100ELT23 front-end.  The
circuit is trivial -- a single SOIC-8 plus bypass cap.
(*) Schematic says 74AC14.
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