[time-freq] Announcing the TADD-3 Pulse Distribution Amplifier

[Christopher T. Day]

John,

I was wondering, could you do what you need for the TADD-2 with the
RefLock II platform? That's a PLL only because of the configuration file
loaded into it. Otherwise, it looks like it could do a divider pretty
easily. I'm probably missing something, and maybe you could explain what
it is. Thanks.


	Chris - AE6VK


-----Original Message-----
From: John Ackermann N8UR [mailto:jra at febo.com] 
Sent: Saturday, May 06, 2006 4:44 AM
To: TAPR time and frequency projects
Subject: Re: [time-freq] Announcing the TADD-3 Pulse Distribution
Amplifier

Christopher T. Day said the following on 05/06/2006 12:49 AM:
> What is/was/will be the TADD-2?
> 
> 
> 	Chris - AE6VK

The TADD-2 is "will be" and is almost "is"...

It's a divider board that accepts standard inputs from 100kHz through
10MHz, and outputs 1pps as well as several other divided frequencies.
It's based on a Xilinx CPLD (Complex Programmable Logic Device) which
allows lots of flexibility in the inputs and outputs.

It was actually the original idea for the TADD series, but got put
behind because I had an immediate need in my lab for the RF amplifier
and 1PPS distribution.  I'm back to working on it now and hope to have a
prototype running "soon".

As a sort of pre-announcement, I will be looking for one or more
volunteers who are familiar with VHDL and ideally the Xilinx CPLD
devices because my initial code is probably quite suboptimal -- I've
never done VHDL before.  So, I'll be prepared to send an alpha or beta
unit to someone who's willing to optimize the code.

John

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