[time-freq] RE: time-freq Digest, Vol 7, Issue 10
Christopher Hoover ch at murgatroid.comFri May 19 21:43:45 UTC 2006
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> Actually, I wouldn't be apposed to added these features you mention > on future Reflock II revisions. Can you give me an idea of what is needed? John (N8UR) originally conceived the project, so I hope he'll speak up and give his opinions. As far as I know there is no formal marketing requirement document (MRD). Here are my two cents: The input sections to Reflock II are quite nice. If you were going to do a bigger board, another of those inputs would be welcome. It would be nice to be able to input drive a few of the CPLD inputs directly. If the CPLD can do it and the pins are chosen carefully, it would be great to be able to support diff psuedo ECL -- is not uncommon on find this on high quality frequency references, especially on telco gear. The main thing Reflock II needs is more outputs. The common case we're discussing is this: an input of 10 MHz (from your house standard) and outputs from a selection of 5 MHz, 1 MHz, 100 KHz, 10 KHz, 1 KHz, 100 Hz, 10 Hz, 1 Hz and 1 PPS (i.e. not 50% duty cycle). Six or so outputs would be plenty, as long as there is a convenient configuration mechanism (e.g., smt dip switches). Output flavors of interest include 1 Vpp into 50Z, TTL, perhaps RS232 levels, perhaps diff PECL. We could live with just good 1 Vpp into 50Z ouputs with fast rise times. E.g., the RS232 levels can happen on TADD-3. -- christopher.
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