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[time-freq] FW: Reflock ll Board

Mike Suhar msuhar at woh.rr.com
Mon Sep 4 15:37:25 UTC 2006

I don't think the LEDs are configured on r2_flex_01.  Looking at the "pin"
file it does not appear they are connected. I think they only come into play
with the PPS files.  My LEDs don't function but the board is working as it

I am running the same version but locking to 114.200 MHz with the same
reference divide by 50.  I will try the same measurement on mine and let you
know what I find. 


-----Original Message-----
From: time-freq-bounces at lists.tapr.org
[mailto:time-freq-bounces at lists.tapr.org] On Behalf Of Rick Hambly (W2GPS)
Sent: Sunday, September 03, 2006 7:56 PM
To: 'TAPR time and frequency projects'
Subject: [time-freq] FW: Reflock ll Board


Can you help with Reflock II questions?

I am trying to help Richard (KB0EMR) by assembling his Reflock II board,
programming it and then testing it for him.

I have it all together and it doesn’t work. The tuning voltage stays stable
regardless of the VCXO frequency and the LEDs never come on.

I have programmed the board with r2_flex_01. I am feeding it with a 10MHz
derived from an HP5065A Rubidium standard and the VCXO signal is 142 MHz
(adjustable) from an HP 8640B signal generator.  I have selected PD1 (XOR
PLL) and have set R=000100 (div by 50) and N=0001000111010 (div by 710).
This should give me a 200 KHz phase comparator. 

Looking with a 200MHz digital scope I see that the VCXO signal is too low at
the collector of U2 (“VCXO”). At 142 MHz the input circuit (Q1/Q2) has
negative gain. I am simulating the VCXO signal with an HP8640B signal
generator. When I adjust the frequency I see that the Reflock II input
circuit rolls off significantly above 50MHz so that it will not adequately
drive the CPLD.  Is this expected behavior? What is the upper limit for the
VCXO input?  The documentation is very sketchy.


I tested the LEDs. They both work and are installed in the correct

Freq MHz   VCXO IN      Col Q2 (VCXO)
  030     1.5 V p-p   2.2 V p-p, min 0V
  050     1.5 V p-p   2.2 V p-p. min 0V
  100     1.5 V p-p   1.1 V p-p, min 0.56V
  140     1.5 V p-p   0.9 V p-p, min 0.70V

The input level was chosen at 30 MHz to be the minimum that produced a nice
looking output to drive the CPLD. Raising the input levels at 100 and 140
MHz produced no improvement in output levels.


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